
/* verilator lint_off UNDRIVEN */
/* verilator lint_off UNUSED */
`include "defines.v"
// `include "ff.v"

module mem_stage(
    input wire clk,
    input wire rst,
    input wire [`REG_BUS-1 : 0] result_ALU,
    input wire [         4 : 0] rd,
    input wire                  w_rd_ena,
    input wire                  load_ena_i,
    input wire                  store_ena_i,
    input wire [         2 : 0] load_store_bytes_i,
    input wire [`REG_BUS-1 : 0] dmem_r_data,
    input wire [`REG_BUS-1 : 0] rs2_data_i,
    input wire                  is_AL_OP_i,
    input wire                  is_B_i,
    input wire                  is_U_i,
    input wire                  is_jal_i,
    input wire                  is_jalr_i,
    input wire                  is_B_jump_i,
    input wire [`REG_BUS-1 : 0] pc_plus_i,
    
    output wire [        4 : 0] rd_o,
    output wire                 w_rd_ena_o,
    output wire [`REG_BUS-1 : 0] wb_data,
    output wire [`REG_BUS-1 : 0] result_ALU_o,
    output wire                  load_ena_o,
    // output wire                  dmem_r_ena,
    // output wire [`REG_BUS-1 : 0] dmem_r_addr,
    // output wire                  dmem_w_ena,
    // output wire [`REG_BUS-1 : 0] dmem_w_addr,
    // output wire [`REG_BUS-1 : 0] dmem_w_data,
    output wire                  is_AL_OP_o,
    output wire                  is_jal_o,
    output wire                  is_jalr_o,
    output wire                  is_U_o,
    output wire                  stall,
    output wire                  is_misalign,
    output wire [         2 : 0] r_addr_2_0,
    output wire [         2 : 0] load_store_bytes_o,
    output wire                  flush,
    output wire [`REG_BUS-1 : 0] pc_plus_o,
    output wire [`REG_BUS-1 : 0] jalr_pc_o
);

    
    
    assign stall = ;




    ff #(.WIDTH( 5)) ff_rd(.clk(clk), .rst(rst), .stall(1'b0), .d(rd), .q(rd_o));
    ff #(.WIDTH( 1)) ff_w_rd_ena(.clk(clk), .rst(rst),.stall(1'b0), .d(w_rd_ena & (~stall)), .q(w_rd_ena_o));

    wire [`REG_BUS-1 : 0] wb_data_wire;
    assign wb_data_wire = dmem_r_data;//load_ena_i ? dmem_r_data : result_ALU;
    ff #(.WIDTH(`REG_BUS)) ff_wb_data(.clk(clk), .rst(rst),.stall(1'b0), .d(wb_data_wire), .q(wb_data));
    // ff #(.WIDTH(`REG_BUS)) ff_wb_data_1(.clk(clk), .rst(rst),.stall(1'b0), .d(wb_data), .q(wb_data_1));
    ff #(.WIDTH(`REG_BUS)) ff_result_ALU(.clk(clk), .rst(rst),.stall(1'b0), .d(result_ALU), .q(result_ALU_o));

    ff #(.WIDTH( 1)) ff_load_ena(.clk(clk), .rst(rst),.stall(1'b0), .d(load_ena_i), .q(load_ena_o));
    ff #(.WIDTH( 1)) ff_is_AL_OP(.clk(clk), .rst(rst),.stall(1'b0), .d(is_AL_OP_i), .q(is_AL_OP_o));

    ff #(.WIDTH( 1)) ff_is_jal(.clk(clk), .rst(rst),.stall(1'b0), .d(is_jal_i), .q(is_jal_o));
    ff #(.WIDTH( 1)) ff_is_jalr(.clk(clk), .rst(rst),.stall(1'b0), .d(is_jalr_i), .q(is_jalr_o));
    ff #(.WIDTH( 1)) ff_is_U(.clk(clk), .rst(rst),.stall(1'b0), .d(is_U_i), .q(is_U_o));

    assign flush = (is_B_jump_i & is_B_i) | is_jalr_i;
    assign pc_plus_o = pc_plus_i;
    assign jalr_pc_o = result_ALU;

endmodule
